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CS4396
24-Bit, 192 kHz D/A Converter for Digital Audio
Features
l 24
Description
The CS4396 is a complete high performance 24-bit 48/96/192 kHz stereo digital-to-analog conversion system. The device includes a digital interpolation filter followed by a oversampled multi-bit delta-sigma modulator which drives dynamic-element-matching (DEM) selection logic. The output from the DEM block controls the input to a multi-element switched capacitor DAC/lowpass filter, with fully-differential outputs. This multi-bit architecture features significantly lower out-of-band noise and jitter sensitivity than traditional 1-bit designs, and the advanced DEM guarantees low noise and distortion at all signal levels. ORDERING INFORMATION CS4396-KS -10 to 70 C 28-pin Plastic SOIC CDB4397 Evaluation Board
Bit Conversion l Up to 192 kHz Sample Rates l 120 dB Dynamic Range l -100 dB THD+N l Advanced Dynamic-Element Matching l Low Clock Jitter Sensitivity l Digital De-emphasis for 32 kHz, 44.1 kHz and 48 kHz l External Reference Input
I
SCLK LRCK SDATA SERIAL INTERFACE AND FORMAT SELECT SOFT MUTE DE-EMPHASIS FILTER
INTERPOLATION FILTER MCLK CLOCK DIVIDER
MULTI-BIT MODULATOR
DYNAMIC ELEMENT MATCHING LOGIC
SWITCHED CAPACITOR-DAC AND FILTER
AOUTL+ AOUTL-
INTERPOLATION FILTER
MULTI-BIT MODULATOR
DYNAMIC ELEMENT MATCHING LOGIC
SWITCHED CAPACITOR-DAC AND FILTER
AOUTR+ AOUTR-
HARDWARE MODE CONTROL (CONTROL PORT)
VOLTAGE REFERENCE
M4 M3 M2 M1 (AD0/CS) (AD1/CDIN) (SCL/CCLK)
M0 RESET (SDA/CDOUT)
MUTEC MUTE
FILT+
VREF
FILT-
CMOUT
Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
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TABLE OF CONTENTS
1.0 CHARACTERISTICS/SPECIFICATIONS ..................................................................... 4 ANALOG CHARACTERISTICS................................................................................... 4 Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz ...................... 4 Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz .................... 4 Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz ..................... 4 ANALOG CHARACTERISTICS................................................................................... 5 Power Supplies .................................................................................................... 5 Analog Output ...................................................................................................... 5 Combined Digital and On-chip Analog Filter Response - Single Speed Mode .... 6 Combined Digital and On-chip Analog Filter Response - Double Speed Mode ... 6 Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode ..... 6 DIGITAL CHARACTERISTICS.................................................................................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................................. 7 RECOMMENDED OPERATING CONDITIONS .......................................................... 7 SWITCHING CHARACTERISTICS ............................................................................. 8 SWITCHING CHARACTERISTICS - CONTROL PORT ............................................. 9 I2C(R) Mode ............................................................................................................ 9 SPI Mode ........................................................................................................... 10 2.0 TYPICAL CONNECTION DIAGRAM .......................................................................... 11 3.0 REGISTER DESCRIPTION ........................................................................................ 12 3.1 Differential DC offset calibration ........................................................................ 12 3.2 Soft Mute ........................................................................................................... 12 3.3 Mode Select ....................................................................................................... 13 3.4 Power DowN ...................................................................................................... 13 4.0 PIN DESCRIPTION ..................................................................................................... 14 5.0 APPLICATIONS .......................................................................................................... 19 5.1 Recommended Power-up Sequence ................................................................. 19 6.0 CONTROL PORT INTERFACE .................................................................................. 20 6.1 SPI Mode ........................................................................................................... 20 6.2 I2C Mode ........................................................................................................... 20 6.2 Memory Address Pointer (MAP) ........................................................................ 20 7.0 PARAMETER DEFINITIONS ...................................................................................... 26 8.0 REFERENCES ............................................................................................................ 26 9.0 PACKAGE DIMENSIONS ........................................................................................... 27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
"The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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TABLE OF FIGURES
Figure 1. Serial Audio Input Timing ........................................................................... 8 Figure 2. I2C Control Port Timing .............................................................................. 9 Figure 3. SPI Control Port Timing ........................................................................... 10 Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode) ....... 11 Figure 5. Control Port Timing, I2C Mode ................................................................. 21 Figure 6. Control Port Timing, SPI mode ................................................................ 21 Figure 7. Single-speed Transition Band .................................................................. 23 Figure 8. Single-speed Stopband Rejection ............................................................ 23 Figure 9. Single-speed Transition Band .................................................................. 23 Figure 10.Single-speed Frequency Response ......................................................... 23 Figure 11.Double-speed Stopband .......................................................................... 23 Figure 12.Double-speed Transition Band ................................................................. 23 Figure 13.Double-speed Transition Band ................................................................. 23 Figure 14.Double-speed Frequency Response ........................................................ 23 Figure 15.Quad-speed Stopband Rejection ............................................................. 24 Figure 16.Quad-speed Transition Band ................................................................... 24 Figure 17.Quad-speed Transition Band ................................................................... 24 Figure 18.Quad-speed Frequency Response .......................................................... 24 Figure 19.De-Emphasis Curve ................................................................................. 24 Figure 20. Format 0, Left Justified ............................................................................ 25 Figure 21. Format 1, I2S .......................................................................................... 25 Figure 22. Format 2, Right Justified, 16-Bit Data ..................................................... 25 Figure 23.Format 3, Right Justified, 24-Bit Data ...................................................... 25
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1.0 CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = DGND;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Test load RL = 1 k, CL = 10 pF) Parameter Symbol Min Typ Max Unit
Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz Dynamic Range (Note 1) TBD 24-Bit unweighted TBD A-Weighted 16-Bit unweighted (Note 2) A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz Dynamic Range (Note 1) TBD 24-Bit unweighted TBD A-Weighted TBD 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz Dynamic Range (Note 1) TBD 24-Bit unweighted TBD A-Weighted TBD 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted Total Harmonic Distortion + Noise (Note 1) THD+N 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB
Notes: 1. Triangular PDF dithered data. 2. Performance limited by 16-bit quantization noise. 4
117 120 95 98 -100 -97 -57 -95 -75 -35
TBD TBD TBD -
dB dB dB dB dB dB dB dB dB dB
117 120 114 92 98 -100 -97 -57 -95 -75 -35
TBD TBD TBD -
dB dB dB dB dB dB dB dB dB dB dB
117 120 114 92 98 -100 -97 -57 -95 -75 -35
TBD TBD TBD -
dB dB dB dB dB dB dB dB dB dB dB
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ANALOG CHARACTERISTICS (Continued)
Parameter Symbol Min normal operation normal operation power-down state normal operation power-down (Note 3) (120 Hz) PSRR IA ID ID + IA VD = 3 V Typ 20 TBD 60 TBD 0.3 60 40 Min TBD RL CL (1 kHz) 1 Max Min TBD TBD TBD Typ 1.4VREF 0.5VREF 0.1 100 2.0 90 VD = 5 V Typ 20 TBD 30 TBD 0.3 60 40 Max TBD TBD 100 Max TBD TBD TBD mA mA A mW mW dB dB Unit Vpp VDC dB ppm/C mV k pF dB Unit
Power Supplies
Supply Current VA = 5 V Power Dissipation VA = 5 V
Power Supply Rejection Ratio (1 kHz)
Parameter
Symbol
Analog Output Full Scale Differential Output Voltage Common Mode Voltage Interchannel Gain Mismatch Gain Drift Differential DC Offset AC-Load Resistance Load Capacitance Interchannel Isolation
Notes: 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing the capacitance will also increase the PSRR.
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ANALOG CHARACTERISTICS
(Continued) Max Unit
Parameter Symbol Min Typ Combined Digital and On-chip Analog Filter Response - Single Speed Mode Passband (Note 4) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz -.020 Passband Ripple StopBand .5465 StopBand Attenuation (Note 5) 102 Group Delay (Note 6) tgd 37/Fs De-emphasis Error (Note 7) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz Combined Digital and On-chip Analog Filter Response - Double Speed Mode Passband (Note 4) to -0.1 dB corner 0 to -3 dB corner 0 Frequency Response 10 Hz to 20 kHz -0.017 Passband Ripple StopBand .570 StopBand Attenuation (Note 5) 82 Group Delay tgd 20/Fs Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode Passband (Note 4) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz 0 Passband Ripple StopBand 0.635 StopBand Attenuation (Note 5) 83 Group Delay tgd 11/Fs
0.470 0.492 +0.015 0.0001 0.10 0.10 0.13
Fs Fs dB dB Fs dB s dB dB dB
0.448 0.486 0.035 0.0008 -
Fs Fs dB dB Fs dB s
0.385 0.472 +0.015 0.00065 -
Fs Fs dB dB Fs dB s
Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-18) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 5. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs. 6. Group Delay for Fs=48 kHz 37/48 kHz=770 s 7. De-emphasis is available only in Single Speed Mode.
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DIGITAL CHARACTERISTICS (TA = 25C; VD =
Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current VD = 5 V VD = 3 V VD = 5 V VD = 3 V 3.0V - 5.25V) Symbol VIH VIL Iin Min 2.0 2.0 Typ 8 3 Max 0.8 0.8 10 Units V V V V A pF mA
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
Parameter DC Power Supply: Positive Analog Positive Digital Reference Voltage Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Symbol VA VD VREF Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 VA 10 (VD)+0.4 125 150 Unit V V V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground)
Parameter DC Power Supply: Positive Digital Positive Analog Reference Voltage Specified Temperature Range Symbol VD VA VREF TA Min 3.0 4.75 TBD -10 Typ 3.3 5.0 5.0 Max 5.25 5.25 VA 70 Unit V V V C
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SWITCHING CHARACTERISTICS (TA= -10 to 70C; Logic 0 = AGND = DGND; Logic
1 = VD = 5.25 to 3.0 Volts; CL = 20 pF) Parameter Input Sample Rate (Single-speed mode) (Double-speed mode) (Quad-speed mode) Symbol Fs Fs Fs Min 16 50 100 45 4.096 6.144 8.192 12.288 40 20 20 20 20 Typ 50 50 Max 50 100 200 55 12.8 19.2 25.6 38.4 60 256xFs 128xFs 64xFs Unit kHz kHz kHz % MHz MHz MHz MHz % Hz Hz Hz ns ns ns ns
LRCK Duty Cycle MCLK Frequency (Single-speed 256 Fs, Double speed 128 Fs or Quad-speed 64 Fs) MCLK Frequency (Single-speed 384 Fs, Double speed 192 Fs or Quad-speed, 96 Fs MCLK Frequency (Single-speed 512 Fs, Double speed 256 Fs or Quad-speed, 128 Fs MCLK Frequency (Single-speed 768 Fs, Double speed 384 Fs or Quad-speed, 192 Fs MCLK Duty Cycle SCLK Frequency (Single-speed mode) (Double-speed mode) (Quad-speed mode) SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time
tslrd tslrs tsdlrs tsdh
LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs
SDATA
t sdh
Figure 1. Serial Audio Input Timing
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SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF) Parameter Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 8) thdd tsud tr tf tsusp Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 Unit KHz ns s s s s s s ns s ns s
I2C(R)
Mode SCL Clock Frequency
RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition
Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 2. I2C Control Port Timing
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SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF) Parameter Symbol fsclk tsrs (Note 9) tspi tcsh tcss tscl tsch tdsu (Note 10) (Note 11) (Note 11) tdh tr2 tf2 tov Min 500 500 1.0 20 66 66 40 15 45 Max 6 100 100 Unit MHz ns ns s ns ns ns ns ns ns ns ns
SPI Mode CCLK Clock Frequency
RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN CCLK Falling to CDOUT valid
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For FSCK < 1 MHz
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 3. SPI Control Port Timing
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2.0 TYPICAL CONNECTION DIAGRAM
+ 1 F
0.1 F 7 VD M0 M1
1.0 F 0.1 f +
+5V Analog
8
5 Mode Select 14 4 3
22 VA
VREF 28
+5V Analog
0.1 f
M2 M3 M4
CS4396
FILT+ 27
+ 10 f
FILT- 26
24
2
AOUTL12
11 Audio Data Processor 13 15 LRCK
Analog Conditioning AOUTL+ 23
SCLK
SDATA
MUTEC 17
AOUTR19
MUTE
Analog Conditioning AOUTR+ 20
1
10
16
RST
MCLK
C/H
DGND 9 6
CMOUT 25
AGND 18 21
0.1 f
+ 10 f
External Clock
Figure 4. Typical Connection Diagram - Hardware Mode (Control Port Mode)
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3.0 REGISTER DESCRIPTION
3.1 DIFFERENTIAL DC OFFSET CALIBRATION
Mode Control Register (address 01h)
7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN
Access:
R/W in I2C and SPI.
Default:
0 - Disabled
Function:
Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be automatically reset following completion of the calibration sequence. CAL 0 1 MODE Disabled : CAL complete Enabled : CAL initiated Table 1. 3.2 SOFT MUTE
Mode Control Register (address 01h)
7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN
Access:
R/W in I2C and SPI.
Default:
0 - Enabled
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC will go low at the completion of the ramp period. The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE. MUTE 0 1 MODE Enabled Disabled Table 2.
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3.3 MODE SELECT
Mode Control Register (address 01h)
7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN
Access:
R/W in I2C and SPI.
Default:
00000
Function:
The Mode Select pins determine the operational mode of the device as detailed in Tables 7-10. The options include: Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 20-23 Selection of the standard 15 s/50 s digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. Selection of the appropriate clocking mode to match the input sample rates. 3.4 POWER DOWN
Mode Control Register (address 01h)
7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN
Access:
R/W in I2C and SPI.
Default:
1 - Powered Down
Function:
The analog and digital sections will be placed into a power-down mode when this function is enabled. This bit must be cleared to resume normal operation. PDN 0 1 MODE Disabled Enabled Table 3.
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4.0 PIN DESCRIPTION
Reset RST See Description M4(AD0/CS) See Description M3(AD1/CDIN) See Description M2(SCL/CCLK) See Description M0(SDA/CDOUT) Digital Ground DGND Digital Power VD Digital Power VD Digital Ground DGND Master Clock MCLK Serial Clock SCLK Left/Right Clock LRCK Serial Data SDATA See Description M1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VREF FILT+ FILTCMOUT AOUTLAOUTL+ VA AGND AOUTR+ AOUTRAGND MUTEC C/H MUTE Voltage Reference Reference Filter Reference Ground Common ModeS Voltage Differential Output Differential Output Analog Power Analog Ground Differential Output Differential Output Analog Ground Mute Control Control port/Hardware select Soft Mute
Reset - RST
Pin 1, Input Function:
The device enters a low power mode and all internal state machines registers are reset when low. When high, the device will be in a normal operation mode . RST 0 1 DESCRIPTION Enabled Normal operation mode
Digital Ground - DGND
Pins 6 and 9, Inputs Function: Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input Function: Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input Function:
The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x 128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample rates and the required master clock frequencies.
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Sample Rate (kHz) 32 44.1 48 MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760
256x 8.1920 11.2896 12.2880
768x 24.5760 33.8688 36.8640
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 128x 8.1920 11.2896 12.2880 192x 12.2880 16.9344 18.4320 256x 16.3840 22.5792 24.5760 384x 24.5760 33.8688 36.8640
Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 176.4 192 Serial Clock - SCLK 64x 11.2896 12.2880 MCLK (MHz) 96x 128x 16.9344 22.5792 18.4320 24.5760 192x 33.8688 36.8640
Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
Pin 11, Input Function:
Clocks individual bits of serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by either the Mode Control Byte in Control Port Mode or the M0 - M4 pins in Hardware Mode. The options are detailed in Figures 20-23 Left/Right Clock - LRCK
Pin 12, Input Function: The Left/Right clock determines which channel is currently being input on the serial audio data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-23
Serial Audio Data - SDATA
Pin 13, Input Function:
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed inin Figures 20-23 Soft Mute - MUTE
Pin 15, Input Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
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cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC will go active at the completion of the ramp period. The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will release immediately on setting MUTE = 1. The converter analog outputs will mute when enabled. The bias voltage on the outputs will be retained and MUTEC will go active during the mute period. Mute 0 1 DESCRIPTION Enabled Normal operation mode
Control Port / Hardware Mode Select - C/H
Pin 16, Input Function: Determines if the device will operate in either the Hardware Mode or Control Port Mode.
C/H 0 1 DESCRIPTION Hardware Mode Enabled Control Port Mode Enabled
Mute Control - MUTEC
Pin 17, Output Function:
The Mute Control pin goes low during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Analog Ground - AGND
Pins 18 and 21, Inputs Function: Analog ground reference.
Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+
Pins 19, 20, 23 and 24, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table.
Analog Power - VA
Pin 22, Input Function: Power for the analog and reference circuits. Typically 5VDC.
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Common Mode Voltage - CMOUT
Pin 25, Output Function:
Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 4. CMOUT has a typical source impedence of 25 k and any current drawn from this pin will alter device performance Reference Ground - FILT-
Pin 26, Input Function: Ground reference for the internal sampling circuits. Must be connected to analog ground.
Reference Filter - FILT+
Pin 27, Output Function:
Positive reference for internal sampling circuits. External capacitors are required from FILT+ to analog ground, as shown in Figure 4. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current. Voltage Reference Input- VREF
Pin 28, Input Function: Analog voltage reference. Typically 5VDC.
HARDWARE MODE Mode Select - M0, M1, M2, M3, M4
Pins 2, 3, 4, 5 and 14, Inputs Function:
The Mode Select pins determine the operational mode of the device as detailed in Tables 7-10. The options include; Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 20-23 Selection of the standard 15 s/50 s digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. Selection of the appropriate clocking mode to match the input sample rates. CONTROL PORT MODE Address Bit 0 / Chip Select - AD0 / CS
Pin 2, Input Function: In I2C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
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Address Bit 1 / Control Data Input - AD1/CDIN
Pin 3, Input Function:
In I2C mode, AD1 is a chip address bit. CDIN is the control data input line for the control port interface in SPI mode. Serial Control Interface Clock - SCL/CCLK
Pin 4, Input Function:
In I2C mode, SCL clocks the serial control data into or from SDA/CDOUT. In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT. Serial Control Data I/O - SDA/CDOUT
Pin 5, Input/Output Function:
In I2C mode, SDA is a data input/output. CDOUT is the control data output for the control port interface in SPI mode. M1 - Mode Select
Pin 14, Input Function:
This pin is not used in Control Port Mode and must be terminated to ground.
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5.0 APPLICATIONS 5.1 Recommended Power-up Sequence
1. Hold RST low until the power supplies, master, and left/right clocks are stable. 2. Bring RST high.
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6.0 CONTROL PORT INTERFACE
The control port is used to load all the internal settings of the CS4396. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4396 operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VD or DGND. If the CS4396 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected.
6.1 SPI Mode
In SPI mode, CS is the CS4396 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data is clocked on the rising edge of CCLK. Figure 5 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W). The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data which will be placed into the register designated by the MAP.
6.2 I2C Mode
In I2C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 2. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the first byte sent to the CS4396, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. For more information on I2C, please see "The I2C-Bus Specification: Version 2.0", listed in the References section. Memory Address Pointer (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 MAP2 0 1 MAP1 0 0 MAP0 1
INCR (Auto MAP Increment Enable) Default = `0' 0 - Disabled 1 - Enabled
MAP0-2 (Memory Address Pointer) Default = `001'
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CS4396
CS CCLK CHIP ADDRESS CDIN
0010000
R/W
MAP
MSB
DATA
LSB
byte 1 MAP = Memory Address Pointer = 0
byte n
Figure 5. Control Port Timing, SPI mode
Note 1 SDA
001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL Start Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 6. Control Port Timing, I2C Mode
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CS4396
M4 0 0 0 0 M4 0 0 0 0 M1 (DIF1) 0 0 1 1 M3 (DEM1) 0 0 1 1 M0 (DIF0) 0 1 0 1 M2 (DEM0) 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data FORMAT 0 1 2 3 FIGURE 20 21 22 23 FIGURE 19 19 19 -
Table 7. Single Speed (16 to 50 kHz) Digital Interface Format Options DESCRIPTION 32 kHz De-Emphasis 44.1 kHz De-Emphasis 48 kHz De-Emphasis De-Emphasis Disabled
Table 8. Single Speed (16 to 50 kHz) De-Emphasis Options M4 1 1 1 1 M3 1 1 1 1 M2 1 1 1 1 M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION Left Justified up to 24-bit data, Format 0 I2S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3
Table 9. Double Speed (50 to 100 kHz) Sample Rate Mode Options M4 1 1 1 1 M3 1 1 1 1 M2 0 0 0 0 M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION Left Justified up to 24-bit data, Format 0 I2S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3
Table 10. Quad (100 to 200 kHz) Sample Rate Mode Options
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0 -20 -40 Amplitude dB
Amplitude dB
0 -20 -40 -60 -80 -100 -120 -140 -160 0.45
-60 -80 -100 -120 -140 -160 0.46 0.48 0.52 0.56 0.58 0.6 0.45 0.46 0.47 0.48 0.49 0.50.50 0.52 0.53 0.540.54 0.56 0.57 0.58 0.59 0.6 0.51 0.55 Frequency (normalized to Fs)
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
Frequency (normalized to Fs)
Figure 7. Single-speed Transition Band
0 -1 -2 Amplitude dB Amplitude dB -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1
Figure 8. Single-speed Stopband Rejection
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 9. Single-speed Transition Band
0 -20 Amplitude dB Amplitude dB -40 -60 -80 -100 -120 -140 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 Frequency (normalized to Fs)
Figure 10. Single-speed Frequency Response
0 -20 -40 -60 -80 -100 -120 -140 0.4 0.45 0.5 Frequency (normalized to Fs) 0.55 0.6
Figure 11. Double-speed Stopband
0 -1 -2 Amplitude dB Amplitude dB -3 -4 -5 -6 -7 -8 -9 -10 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 0
Figure 12. Double-speed Transition Band
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 13. Double-speed Transition Band DS288PP1
Figure 14. Double-speed Frequency Response 23
CS4396
0 -20 -40 Amplitude dB -60 -80 -100 -120 -140 -160 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 Frequency (normalized to Fs) Amplitude dB 0 -20 -40 -60 -80 -100 -120 -140 -160 0.5 0.52 0.54 0.56 0.58 0.6 0.62 0.64 0.66 0.68 0.7 Frequency (normalized to Fs)
Figure 15. Quad-speed Stopband Rejection
Figure 16. Quad-speed Transition Band
0 -1 -2 Amplitude dB Amplitude dB 0.37 0.39 0.41 0.43 0.45 0.47 0.49 0.51 0.53 -3 -4 -5 -6 -7 -8 -9 -10 0.35
0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (normalized to Fs) Frequency (normalized to Fs)
Figure 17. Quad-speed Transition Band
Figure 18. Quad-speed Frequency Response
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 19. De-Emphasis Curve
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LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 20. Format 0, Left Justified
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 21. Format 1, I2S
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 22. Format 2, Right Justified, 16-Bit Data
LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
32 clocks
Figure 23. Format 3, Right Justified, 24-Bit Data
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CS4396
7.0 PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
8.0 REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4397 Evaluation Board Datasheet 3) "The I2C-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com
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9.0 PACKAGE DIMENSIONS
28L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
DIM A A1 B C D E e H L
INCHES MIN 0.093 0.004 0.013 0.009 0.697 0.29G10 1 0.040 0.394 0.016 0
MAX 0.104 0.012 0.020 0.013 0.713 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.02 10.00 0.40 0 1.52 10.65 1.27 8
JEDEC #: MS-013
DS288PP1
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